Computers and Technology

What is the amat for a system with the following specifications? percentage of instructions accessing memory 36% main memory access time 30 ns size of the l1 cache = 4 kb l1 cache hit rate = 60% l1 hit time 0.6ns size of the l2 cache = 10 mb l2 cache hit rate = 20% l2 hit time 18ns core frequency 3.333ghz

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Computers and Technology, 24.06.2019 23:00, iamPaola
What is the amat for a system with the following specifications? ● percentage of instructions accessing memory = 36% ● main memory access time = 30 ns ● size of the l1 cache = 4 kb ● l1 cache hit rate = 60% ● l1 hit time = 0.6ns ● size of the l2 cache = 10 mb ● l2 cache hit rate = 20% ● l2 hit time = 18ns ● core frequency 3.333ghz show your calculations for full credit.
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Computers and Technology, 13.07.2019 01:20, estheradame547
Consider a demand-paging system with a paging disk that has an average access and transfer time of 50 ms. addresses are translated through a page table in main memory, with an access time of 2 us per memory access. thus, each memory reference through the page table takes two accesses. to improve this time, we have added an associative memory (tlb) that reduces access time to one memory reference, if the page-table entry is in the associative memory (tlb). ssume that 90% of the accesses are in the associative memory (tlb), and that, of the remaining, 20%) or 2% of the total) cause page faults, what is the effective memory access time?
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Computers and Technology, 10.09.2019 19:10, kyleap984ovm04g
You are building a system around a single-issue in-order processor running at 1 ghz and the processor has a base cpi of 1 if all memory accesses are hits. the only instructions that read or write data from memory are loads (20% of all instructions) and stores (5% of all instructions). the memory system for this computer is composed of a split l1 cache that imposes no penalty on hits. both the i-cache and d-cache are direct mapped and hold 32kb each. you may assume the caches use write-allocate and write-back policies. the l1 i-cache has a 2% miss rate and the l1 d-cache has a 5% miss rate. also, 50% of all blocks replaced from l1 d-cache are dirty. the 512kb write-back, unified l2 cache has an access time of 10ns. of all memory references sent to the l2 cache in this system, 80% are satisfied without going to main memory. also 25% of all blocks replaced are dirty. the main memory has an access latency of 60ns. a. what is the overall cpi, including memory accesses? b. you are considering replacing the 1 ghz cpu with one that runs at 2 ghz, but is otherwise identical. how much faster does the system run with a faster processor? assume the l1 cache still has no hit penalty, and that the speeds of the l2 cache, and main memory remain the same in absolute terms (e. g. the l2 cache still has a 10 ns access time).
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Computers and Technology, 07.11.2019 03:31, whocares1234
You are building a system around a single-issue in-order processor running at 2 ghz and the processor has a base cpi of 1 if all memory accesses are hits. the only instructions that read or write data from memory are loads (20% of all instructions) and stores (5% of all instructions). the memory system for this computer is composed of a split l1 cache that imposes no penalty on hits. both the i-cache and d-cache are direct mapped and hold 32kb each. you may assume the caches use write-allocate and write-back policies. the l1 i-cache has a 2% miss rate and the l1 d-cache has a 5% miss rate. also, 50% of all blocks replaced from l1 d-cache are dirty. the 512kb write-back, unified l2 cache has an access time of 12ns. of all memory references sent to the l2 cache in this system, 80% are satisfied without going to main memory. also 25% of all blocks replaced are dirty. the main memory has an access latency of 60ns. a. what is the overall cpi, including memory accesses?
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